EUVL process structure fabrication methods
US8865376B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/22
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.