3D semiconductor package interposer with die cavity
US8865521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.