Fully depleted SOI multiple threshold voltage application
US8865539B2 · kind B2 · utility
11Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.