Ge-based NMOS device and method for fabricating the same
US8865543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Feb 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.