Device and methods for forming partially self-aligned trenches
US8865595B2 · kind B2 · utility
8Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 5, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Nov 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.