Construction of reliable stacked via in electronic substrates—vertical stiffness control method
US8866026B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.