Semiconductor packages and methods of formation thereof
US8866274B2 · kind B2 · utility
5Cited by
22References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.