Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact
US8866507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Sep 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated accordi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.