SRAM read-write memory cell having ten transistors
US8867264B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 14, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.