Repairable multi-layer memory chip stack and method thereof
US8867286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.