Memory arbitration circuitry
US8867303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jan 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.