Implementing storage adapter performance optimization with cache data/directory mirroring
US8868828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.