Virtual memory management for real-time embedded devices
US8868883B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Mar 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.