Testing and operating a multiprocessor chip with processor redundancy
US8868975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.