Patent · US Active

System for testing error detection circuits

US8868989B2 · kind B2 · utility

5Cited by

12References

17Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Amit Jindal · Palo Alto, US
Nitin Singh · Bengaluru, IN

Key dates

Filing date	Jul 12, 2012
Grant date	Oct 21, 2014
Priority date	—
Expiry date	Feb 7, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/556
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.