Three dimensional (3D) memory device sparing
US8869007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jul 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.