Mask formation processing
US8871651B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask for use in fabricating one or more semiconductor devices is fabricated by: providing sacrificial spacing structures disposed over a substrate structure, and including protective hard masks at upper surfaces of the spacing structures; disposing a sidewall spacer layer conformally over the sacrificial spacing structures; selectively removing the sidewall spacer layer from above the sacrificial spacing structures to expose the protective hard masks of the spacing structures, the selectively removing including leaving sidewall spacers along sidewalls of the sacrificial spacing structures; providing a protective material over the substrate structure; and removing the exposed protective hard masks from the sacrificial spacing structures, and thereafter, removing remaining sacrificial spacing structures and the protective material, leaving the sidewall spacers over the substrate structure as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.