Method and system for program scheduling in a multi-layer memory
US8873284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.