Task queuing in a multi-flow network processor architecture
US8873550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | May 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments generate tasks corresponding to each packet received by a network processor. A destination processing module receives a task and determines, based on the task size, a queue in which to store the task, and whether the task is larger than space available within a current memory block of the queue. If the task is larger, an address of a next memory block in a memory is determined, and the address is provided to a source processing module of the task. The source processing module writes the task to the memory based on a provided offset address and the address of the next memory block, if provided. If a task is written to more than one memory block, the destination processing module preloads the address of the next memory block to a local memory to process queued tasks without stalling to retrieve the address of the next memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.