Integrated circuit including a first channel and a second channel
US8877576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2007 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Jan 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.