Semiconductor manufacturing process and structure thereof
US8877629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Jun 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.