Patent · US Active

Providing a void-free filled interconnect structure in a layer of package substrate

US8877632B1 · kind B1 · utility

0Cited by
3References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 13, 2013
Grant dateNov 4, 2014
Priority date—
Expiry dateMay 13, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for providing void-free filled interconnect structures in a dielectric layer of a package assembly. In one embodiment, the method for providing a void-free filled interconnect structure may include forming a through hole through a layer of a package substrate, and depositing a conductive material to fill the through hole. Depositing the conductive material may be performed while gradually increasing a current density of the conductive material and correspondingly changing a flow rate of the conductive material. Other embodiments may be described and/or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.