Methods and apparatus for an ISFET

US8878257B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Patrice M. Parris · Phoenix, US
• Weize Chen · Phoenix, US
• Richard J. De Souza · Tempe, US
• Md M. Hoque · Gilbert, US
• John M. McKenna · Hackettstown, US

Key dates

• Filing date: Jun 4, 2010
• Grant date: Nov 4, 2014
• Expiry date: Jun 1, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.