Semiconductor device having a buffer material and stiffener
US8878350B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.