Disk synchronous write architecture for bit-patterned recording
US8879185B1 · kind B1 · utility
3Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/59616
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, apparatus, and techniques are provided for controlling synchronization of a write clock. A frequency offset is estimated based, at least partially, on a location of the servo synchronization marker to produce the frequency offset estimate. A phase correction value and a frequency correction value associated with the write clock are obtained, and a data clock timing control signal is produced based on the frequency offset estimate, the phase correction value, and the frequency correction value. The data clock timing control signal is applied to a phase interpolator to modify a phase of the write clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.