Magnetic memory circuit with stress inducing layer
US8879306B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2011 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Dec 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.