Method for measuring assertion density in a system of verifying integrated circuit design
US8881075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Mar 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.