Cell-level electrostatic discharge protection for an integrated circuit
US8881085B1 · kind B1 · utility
9Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2010 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.