Method of semiconductor integrated circuit fabrication
US8883403B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Sep 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0332
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.