Method of manufacturing semiconductor device, semiconductor device and multilayer wafer structure
US8883566B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 9, 2014 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Apr 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.