Decoupling composite capacitor in a semiconductor wafer
US8883605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.