Patent · US Active

Clock generator

US8884666B2 · kind B2 · utility

2Cited by

17References

22Claims

0Family size

Assignee

PS4 Luxco S.a.r.l. · LU

Inventors

Marco Passerini · Lozza, IT
Stefano Surico · Milano, IT

Key dates

Filing date	Aug 2, 2011
Grant date	Nov 11, 2014
Priority date	—
Expiry date	Aug 2, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.