System and method for implementing a single chip having a multiple sub-layer PHY
US8886840B2 · kind B2 · utility
7Cited by
20References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/357
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.