Mechanisms to accelerate transactions using buffered stores
US8886894B2 · kind B2 · utility
13Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.