Dynamic memory cache size adjustment in a memory device
US8886911B2 · kind B2 · utility
48Cited by
1References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | May 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.