Methods for forming MOS devices with raised source/drain regions
US8889501B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Jan 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.