Lithographic method for making networks of conductors connected by vias
US8889550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2011 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | May 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.