Via arrangement and semiconductor device with the via arrangement

US8890320B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Shanghai) Corporation · CN
• Semiconductor Manufacturing International (Beijing) Corporation · CN

Inventors

• Jerry Liu · Atlanta, US
• Wanchun Ding · Shanghai, CN
• Wendy Wei · Shanghai, CN

Key dates

• Filing date: Oct 24, 2012
• Grant date: Nov 18, 2014
• Expiry date: Oct 24, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via.