Semiconductor chip layout with staggered Tx and Tx data lines
US8890332B2 · kind B2 · utility
1Cited by
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27Claims
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.