Patent · US Active

Well-biasing circuit for integrated circuit

US8890602B2 · kind B2 · utility

4Cited by

8References

3Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Samaksh Sinha · New Delhi, IN
Manmohan Rana · Ghaziabad, IN
Nishant Singh Thakur · Indore, IN

Key dates

Filing date	Jan 16, 2013
Grant date	Nov 18, 2014
Priority date	—
Expiry date	Mar 14, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG05F3/205
WIPO fieldControl
WIPO sectorInstruments

Abstract

A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.