Reducing write amplification in a flash memory
US8892811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Dec 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having a memory circuit and a manager is disclosed. The memory circuit generally has (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses. The manager may be configured to (i) receive data items in a random order from one or more applications, (ii) write the data items in an active one of a plurality of regions in a memory circuit and (iii) mark the memory addresses in the active region that store the data items as used. Each data item generally has a respective host address. The applications may be executed in one or more computers. The memory addresses in the active region may be accessed in a sequential order while writing the data items to minimize a write amplification. The random order is generally preserved between the data items while writing in the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.