Output control scan flip-flop, semiconductor integrated circuit including the same, and design method for semiconductor integrated circuit
US8892971B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2012 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Jan 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An output control scan flip-flop according to the present invention includes a first scan flip-flop that captures first data in a first mode and second data in a second mode in synchronization with a clock signal to output the data that is captured, a second scan flip-flop that captures the data output from the first scan flip-flop in the second mode in synchronization with a clock signal to output the data that is captured, and a gating circuit that generates the data output from the first scan flip-flop in the first mode as output data, and generates output data having a change rate of a logic value lower than a change rate of a logic value of the data output from the first scan flip-flop based on the data output from each of the first scan flip-flop and the second scan flip-flop in the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.