Patent · US Active

Die preparation for wafer-level chip scale package (WLCSP)

US8895363B2 · kind B2 · utility

3Cited by

0References

6Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Hartmut Buenning · Norderstedt, DE
Sascha Moeller · Hamburg, DE
Guido Albermann · Hamburg, DE
Thomas Rohleder · Hamburg, DE
Michael Zernack · Pinneberg, DE

Key dates

Filing date	Mar 15, 2013
Grant date	Nov 25, 2014
Priority date	—
Expiry date	Mar 15, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/94
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.