Memory device, method of operating the same, and electronic device having the memory device
US8897055B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.