Bandwidth limiting on generated PCIe packets from debug source
US8898359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Feb 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.