Fault handling in address translation transactions
US8898430B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2012 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/073
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.