Layout optimization for integrated design
US8898600B2 · kind B2 · utility
3Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Nov 25, 2014 |
| Priority date | — |
| Expiry date | Jul 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.