Yu-Hsiang Kao
7Patents
1h-index
11Co-inventors
40Inventor score
Filing activity: Apr 3, 2012 → Oct 20, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8898600B2 | Layout optimization for integrated design | Physics | 3 | Active |
| US9418196B2 | Layout optimization for integrated circuit design | Emerging Cross-Sectional Technologies | 1 | Active |
| US11865518B2 | Method for manufacturing electroless plating substrate and method for forming metal layer on surface of substrate | Chemistry; Metallurgy | 0 | Active |
| US9754073B2 | Layout optimization for integrated circuit design | Emerging Cross-Sectional Technologies | 0 | Active |
| US9553043B2 | Interconnect structure having smaller transition layer via | Electricity | 0 | Active |
| US9292645B2 | Layout optimization for integrated circuit design | Physics | 0 | Active |
| US10828624B2 | Self-adsorbed catalyst composition, method for preparing the same and method for manufacturing electroless plating substrate | Chemistry; Metallurgy | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.