Patent · US Active

System for placing dummy tiles in metal layers of integrated circuit design

US8898612B1 · kind B1 · utility

2Cited by

3References

14Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Ankit Jain · Mountain View, US
Narayanan Kannan · Delhi, IN

Key dates

Filing date	Oct 30, 2013
Grant date	Nov 25, 2014
Priority date	—
Expiry date	Oct 30, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.