Transistor having doped substrate and method of making the same
US8901609B1 · kind B1 · utility
10Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 17, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A transistor includes a substrate, wherein a top portion of the substrate is doped with p-type dopants to a dopant concentration ranging from about 1×1018 ions/cm3 to about 1×1023 ions/cm3. The transistor further includes a graded layer on the substrate and a channel layer on the graded layer. The transistor further includes an active layer on the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.